LTC4268IDKD-1#PBF【PDF 5/46 页】IC PD HIGH POWER W/CNTRL 32-DFN

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Sheet目录42

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42681fc

LTC4268-1

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

LCOMP

Feedback Pin Load Compensation

Current

RCMP

With V

SENSE

= 0V

礎

LCOMP

Load Comp to V

SENSE

Offset Voltage

SENSE+

= 20mV, V

= 1.23V

UVLO

UVLO Pin Threshold

1.215

1.237

1.265

UVLOL

UVLOH

UVLO Pin Bias Current

UVLO

= 1.2V

UVLO

= 1.3V

0.25

4.50

3.4

0.25

2.5

礎

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 2: All voltages are with respect to V

PORTP

pin unless otherwise noted.

Note 3: Active High PWRGD internal clamp circuit self-regulates to 14V

with respect to V

NEG

. V

has internal 20V clamp with respect to GND.

Note 4: This IC includes overtemperature protection that is intended

to protect the device during momentary overload conditions. Junction

temperature will exceed 125癈 when overtemperature protection is active.

Continuous operation above the specified maximum operating junction

temperature may impair device reliability.

Note 5: T

is calculated from the ambient temperature T

and power

dissipation P

DIS

according to the formula:

= T

+ (P

DIS

" 49癈/W)

Note 6: The LTC4268-1 operates with a negative supply voltage in the

range of 1.5V to 57V. To avoid confusion, voltages in this data sheet

are referred to in terms of absolute magnitude. Terms such as maximum

negative voltage refer to the largest negative voltage and a rising

negative voltage refers to a voltage that is becoming more negative.

Note 7: In IEEE 802.3af systems, the maximum voltage at the PD jack is

defined to be 57V.

Note 8: The LTC4268-1 is designed to work with two polarity protection

diodes in series with the input. Parameter ranges specified in the Electrical

Characteristics are with respect to LTC4268-1 pins and are designed to

meet IEEE 802.3af specifications when the drop from the two diodes is

included. See Applications Information.

Note 9: Signature resistance is measured via the two-point DV/DI method

as defined by IEEE 802.3af. The LTC4268-1 signature resistance is offset

from 25k to account for diode resistance. With two series diodes, the total

PD resistance will be between 23.75k and 26.25k and meet IEEE 802.3af

specifications. The minimum probe voltages measured at the LTC4268-1

pins are 1.5V and 2.5V. The maximum probe voltages are 9.1V and

10.1V.

Note 10: The LTC4268-1 includes hysteresis in the UVLO voltages to

preclude any start-up oscillation. Per IEEE 802.3af requirements, the

LTC4268-1 will power up from a voltage source with 20?series resistance

on the first trial.

Note 11: Supply current does not include gate charge current to the

MOSFETs. See Application Information.

Note 12: To disable the 25k signature, tie SHDN to V

PORTP

(?.1V) or hold

SHDN high with respect to V

. See Applications Information.

Note13: I

LIM_EN

pin is pulled high internally and for normal operation

should be left floating. To disable current limit, tie I

LIM_EN

to V

. See

Applications Information.

Note 14: I

IN_CLASS

does not include classification current programmed at

Pin 3. Total supply current in classification mode will be I

IN_CLASS

+ I

CLASS

(See Note 15).

Note 15: I

CLASS

is the measured current flowing through R

CLASS

. I

CLASS

accuracy is with respect to the ideal current defined as I

CLASS

= 1.237/

CLASS

. T

CLASSRDY

is the time for I

CLASS

to settle to within ?.5% of ideal.

The current accuracy specification does not include variations in R

CLASS

resistance. The total classification current for a PD also includes the IC

quiescent current (I

IN_CLASS

). See Applications Information.

Note 16: This parameter is assured by design and wafer level testing.

Note 17: Active high power good is referenced to V

NEG

and is valid for

PORTP

NEG

e 4V.

Note 18: The LTC4268-1 includes a dual current limit. At turn on, before

C1 is charged, the LTC4268-1 current level is set to I

LIMIT_LOW

. After C1 is

charged and with I

LIM_EN

floating, the LTC4268-1 switches to I

LIMIT_HIGH

With I

LIM_EN

pin tied low, the LTC4268-1 switches to I

LIMIT_DISA

. The

LTC4268-1 stays in I

LIMIT_HIGH

or I

LIMIT_DISA

until the input voltage drops

below the UVLO turn-off threshold or a thermal overload occurs.

Note 19: The LTC4268-1 features thermal overload protection. In the event

of an over temperature condition, the LTC4268-1 will turn off the power

MOSFET, disable the classification load current, and present an invalid

power good signal. Once the LTC4268-1 cools below the over temperature

limit, the LTC4268-1 current limit switches to I

LIMIT_LOW

and normal

operation resumes.

Note 20: I

LIMIT_DISA

is a safeguard current limit that is activated when the

normal input current limit (I

LIMIT_HIGH

) is defeated using the I

LIM_EN

pin.

Currents at or near I

LIMIT_DISA

will cause significant package heating and

may require a reduced maximum ambient operating temperature in order

to avoid tripping the thermal overload protection.

Note 21: Component value range guaranteed by design.

elecTrical characTerisTics

The l denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T

= 25癈. V

= 14V, SG open, V

CMP

= 1.5V, V

SENSE

= 0V, R

CMP

= 1k, R

tON

= 90k,

PGDLY

= 27.4k, R

ENDLY

= 90k, unless otherwise specified.

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